← AXS-047

Circuit review & bench-test guide

AXS-047 — RC522 RFID carrier PMOD module

Document purpose#

This document explains the axs-047-rfid carrier at component level and turns the design evidence into a manual-review and bench-test plan. It is based on generate_design.py, the generated schematic, the README, and the NXP MFRC522 datasheet.

The board is an unfabricated prototype: schematic generated, ERC clean (0/0), netlist reviewed, no PCB layout, no fabricated board, no BOM export, no bench results. Both connector MPNs are TBD:. The plug-in is the generic "RC522 blue board", which ships with an MFRC522 (or a clone of it) — carrier validation is only meaningful against the specific purchased breakout.

1. What the board does#

The carrier hosts the ubiquitous MFRC522 "blue board" 13.56 MHz RFID/NFC reader on a 1×8 socket and maps it to PMOD Type 2A (expanded SPI): ~CS, MOSI, MISO, SCK on pins 1–4, IRQ on pin 7, RST on pin 8. Everything is 3.3 V; the carrier adds series resistors on the two module-driven lines (MISO, IRQ), a 10 k pull-up on RST_N, and socket decoupling for RF transmit bursts. The blue board straps the MFRC522 into SPI mode; its "SDA" pin is the SPI ~SS.

Functional block diagram#

PMOD host (ECP5) J1                      RC522 blue board (plug-in, J2 1x8 socket)
  pin 1 CS_N ───────────────────────────> 1 SDA (SPI ~SS)
  pin 4 SCK ────────────────────────────> 2 SCK
  pin 2 MOSI ───────────────────────────> 3 MOSI
  pin 3 MISO <── R1 100 Ω ──────────────  4 MISO
  pin 7 RFID_IRQ <── R2 100 Ω ──────────  5 IRQ
  pins 5/11 GND ────────────────────────  6 GND
  pin 8 RST_N ──┬───────────────────────> 7 RST   (R3 10 k pull-up to 3V3)
  pins 6/12 3V3 ─┬─ C1 100 nF ─ C2 10 µF  8 3.3V

2. Safety and scope boundaries#

• Electrically this is the tamest carrier in the family: single 3.3 V domain, no external supply. The main hazards are assembly-order errors (section 4) and RF-plane mistakes in layout.
• The MFRC522 transmitter drives the blue board's printed antenna at 13.56 MHz. Emissions are low-power proximity-coupling fields, but the assembled system is not certified to any radio regulation; treat bring-up as engineering evidence only.
• RFID/NFC reading of third-party cards can carry privacy implications; test with your own cards/fobs.
• The blue board's transmit bursts draw up to ~100 mA peaks from 3V3 (ITVDD max) on top of the digital core current — budget the host's PMOD rail.

3. Power and control sequence (design intent)#

1. Host powers the PMOD; 3V3 reaches J2 pin 8; C1/C2 buffer transmit bursts.
2. R3 holds RST high, so the reader boots immediately; the host may hold RST_N low to keep it in hard power-down (NRSTPD low ⇒ ≤5 µA, per datasheet) until wanted.
3. Host configures the MFRC522 over SPI mode 0 (CPOL=0, CPHA=0, MSB first, ≤10 Mbit/s per datasheet; start at ≤1 MHz on the bench).
4. IRQ (module-driven, configurable polarity via the chip's DivIEn/ComIEn registers) returns through R2 for interrupt-driven designs.

4. Plug-in module verification (read before first power)#

Mandatory section. Blue-board clones occasionally deviate from the common pin order, and 3V3 landing on a signal pin — or SDA landing on the 3.3V pad — means no damage-free first power.

4.1 Pin-order check against the breakout silkscreen#

The carrier assumes the common blue-board order:

1 SDA(SS), 2 SCK, 3 MOSI, 4 MISO, 5 IRQ, 6 GND, 7 RST, 8 3.3V

Procedure, with the breakout unplugged and the carrier unpowered:

1. Read the breakout's silkscreen; write the order down. If any name is unreadable, trace: pin 8's track goes to the LDO/3.3 V plane, pin 6 to the ground pour, SDA to MFRC522 pin 24 area (fine-pitch — use the plane checks instead: GND and 3.3V are easy to confirm with a DMM against the crystal can or C pads).
2. On the carrier, buzz J2 position 8 to the PMOD 3V3 pins and position 6 to GND. Then confirm the breakout's own 3.3V and GND pins will land there in the actual insertion orientation.
3. A 1×8 socket is unkeyed and can be plugged backwards: reversed, 3.3 V lands on SDA and SDA on 3.3 V, and SCK/RST cross. Mark the correct orientation on both boards with paint before first power.
4. Confirm the breakout is the SPI-strapped variant (the standard blue board is; I2C/UART-strapped derivatives exist). If in doubt, the version register read in section 9.C settles it — a board that answers on SPI is strapped for SPI.

4.2 Plug-in key specifications (NXP MFRC522, Rev. 3.2 datasheet)#

5. Component-by-component review#

#FLG01/#FLG02 are ERC power flags, not physical parts.

Host-driven lines (CS_N, MOSI, SCK, RST_N drive) are wired directly, matching the family convention: series resistors only on module-driven lines.

6. Datasheet summary and design interpretation#

Official references: MFRC522 datasheet (NXP) (mirror), NXP MFRC522 product page.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Verify the purchased breakout's silkscreen order against J2 (section 4.1) and mark insertion orientation on both boards.
• Confirm R1 is in MISO and R2 in IRQ (module-driven), and that CS/MOSI/SCK are direct.
• Confirm R3 goes to 3V3, not GND.
• Close the two TBD: MPNs; export and availability-check the BOM.
• After layout: keep carrier copper (planes and traces) out of the region under the breakout's antenna end — the README calls this out; verify the keep-out survived layout.
• Socket height: the blue board's components face must clear the carrier.

9. Ordered bench-test procedure#

Stop at the first abnormal result.

A. Unpowered checks#

1. Complete section 4.1 orientation check and mark it.
2. Resistance 3V3-to-GND at the PMOD plug, socket empty, then fitted.
3. Buzz each J2 position to its PMOD pin / net (eight checks).

B. First power, no SPI traffic#

1. Host on. Measure 3V3 at J2 pin 8 and the idle current delta.
2. RST_N reads 3.3 V; drive it low from the host: current drops to the hard-power-down floor (µA-class on the MFRC522 itself; the blue board's LDO/LED may dominate — record the actual number for this breakout).

C. SPI register-map contact — the version read#

1. At ≤1 MHz, SPI mode 0, read VersionReg 0x37: send the read-format address byte (0x37<<1)|0x80 = 0xEE, clock a dummy byte, capture the response. Expect 0x91 (v1.0) or 0x92 (v2.0). Anything else and the board answers but carries clone silicon — record the value; most clones still work for the curriculum.
2. If the read returns 0x00 or 0xFF: check CS framing, R1 path, and the address-byte format (the most common failure is firmware, not hardware).
3. Write/readback test: write TxASKReg or a scratch-usable register (e.g., write 0x25 to ModWidthReg 0x24, read it back), then soft-reset (CommandReg 0x01 = 0x0F) and confirm defaults return.
4. Optional: run the built-in self test (datasheet §16.1.1) and compare the 64-byte signature against the version-appropriate table.

D. RF on and IRQ path#

1. Enable the transmitter (TxControlReg bits Tx1RFEn/Tx2RFEn); watch the supply current step (~+60 mA) — this proves the antenna drive and C2.
2. Configure ComIEnReg for receive interrupts; present a card; confirm the IRQ edge arrives at PMOD pin 7 through R2 and matches the polling result.

E. Card detect range (ISO14443A REQA/anticollision)#

1. Run REQA→ATQA: present a MIFARE Classic card face-parallel to the antenna. Record ATQA.
2. Anticollision + SELECT: read the UID; verify it is stable across 10 presentations.
3. Range: raise the card in 5 mm steps on a non-metallic jig; record the greatest distance with 10/10 successful UID reads. Expect ~20–40 mm; ≥50 mm would exceed the datasheet's own claim — recheck the setup. Metal under the antenna or the carrier's copper (layout keep-out) is the usual cause of gross range loss.
4. Repeat with a keyfob (smaller coupling loop — shorter range is normal).

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

This is the lowest-electrical-risk carrier in the group: one 3.3 V domain, series resistors on both module-driven lines, a sane reset default, and decoupling scaled to the documented 100 mA transmit peaks. The risks that remain are operational: an unkeyed 1×8 socket that accepts a reversed board (3.3 V onto SDA), uncontrolled clone silicon behind the "RC522" name — which the 0x37 version read exposes on first contact — the antenna keep-out that exists only as intent until layout is done, and the absence of any fabrication or bench evidence at this revision.