← AXS-050

Circuit review & bench-test guide

AXS-050 — OV7670 camera carrier dual-PMOD module (flagship)

Document purpose#

This document explains the axs-050-camera carrier at component level and turns the design evidence into a manual-review and bench-test plan. It is based on generate_design.py, the generated schematic, the README, and the OmniVision OV7670 datasheet. This is the flagship (L5) module and the most complex carrier in the line: two PMOD plugs, fifteen resistors, a camera-driven clock domain, and an I2C-compatible control bus.

The board is an unfabricated prototype: schematic generated, ERC clean (0/0), netlist reviewed, no PCB layout, no fabricated board, no BOM export, no bench results. Three connector MPNs are TBD:. The plug-in is the generic 18-pin no-FIFO OV7670 breakout, an uncontrolled commodity part — carrier validation is only meaningful against a specific purchased unit.

1. What the board does#

The carrier hosts an 18-pin OV7670 breakout (VGA CMOS sensor, no FIFO) on a 2×9 socket and fans it out to two adjacent PMOD sockets on the ECP5 host:

• J1 (PMOD A) carries the 8-bit pixel bus D0–D7, all camera-driven, each through 100 Ω series resistors (R1–R8).
• J3 (PMOD B) carries the timing and control set: PCLK (camera-driven, R9), XCLK (host-driven 24 MHz from a fabric PLL, direct), HREF (R10), VSYNC (R11), the SCCB bus SIOC/SIOD with 4.7 k pull-ups (R12/R13), RESET_N with a 10 k pull-up (R14), and PWDN with a 10 k pull-down (R15).

Data flow: the host feeds XCLK, configures the sensor over SCCB (I2C- compatible, 7-bit address 0x21 = write 0x42 / read 0x43), then samples D0–D7 on PCLK edges while HREF is high, framed by VSYNC.

Functional block diagram#

PMOD A (J1)                                OV7670 breakout (J2, 2x9)
  1..4,7..10  D0–D7  <── R1–R8 100 Ω ────  D0–D7 (camera outputs)
PMOD B (J3)
  1 PCLK  <── R9  100 Ω ─────────────────  PCLK  (camera output, up to 24 MHz)
  2 XCLK  ───────────────────────────────> XCLK (host 24 MHz, direct)
  3 HREF  <── R10 100 Ω ─────────────────  HREF
  4 VSYNC <── R11 100 Ω ─────────────────  VSYNC
  7 SIOC ──┬── R12 4.7 k ── 3V3           SIOC (SCCB clock)
  8 SIOD ──┴── R13 4.7 k ── 3V3           SIOD (SCCB data, bidirectional)
  9 RESET_N ──┬─ R14 10 k ── 3V3          RESET (active low)
  10 PWDN ────┬─ R15 10 k ── GND          PWDN (active high)
  3V3 ── C1 100 nF ── C2 10 µF ── GND     VCC / GND

2. Safety and scope boundaries#

• Single 3.3 V domain, no external supply: electrical risk is low. The real hazards are orientation errors across three unkeyed connectors (two PMOD plugs and a 2×9 socket) and out-of-spec I/O levels (section 6).
• The dual-PMOD plug pair mechanically locks the carrier's orientation if the layout pitch matches the host's paired-socket spacing exactly — until layout is verified, treat plugging as a checked step, not a given.
• Camera modules are ESD-sensitive bare-lens assemblies; handle by the PCB, keep the lens capped when not testing.
• Nothing here is imaging-quality qualification. VGA color fidelity, lens focus, and exposure behavior are commodity-breakout properties, not carrier properties.

3. Power and control sequence (design intent)#

The OV7670 has documented power-up ordering requirements at the rail level; on the 18-pin breakout those rails come from the breakout itself, so the carrier-level sequence reduces to control-line ordering:

1. Host powers both PMODs (same 3V3 rail); R14 releases RESET high, R15 holds PWDN low — the camera is powered and out of reset by default.
2. Start XCLK before talking SCCB. The sensor's logic is clocked from XCLK; without a running clock the SCCB interface does not respond dependably. Bring the 24 MHz PLL output up first.
3. Apply a clean reset with the clock running: RESET_N low ≥1 ms, release, then wait ≥1 ms (datasheet t_S:RESET ≤1 ms settling after reset) before the first SCCB transaction.
4. Configure registers over SCCB at ≤400 kHz (datasheet SCCB f_SIO_C max; 100 kHz per the design note). Register changes settle within 300 ms / 10 frames (t_S:REG) — allow it before grading images.
5. Capture: sample D0–D7 on the documented PCLK edge while HREF is high; VSYNC pulses 3×t_LINE at frame start; t_LINE = 784 t_P (VGA); for RGB565/YUV output two bytes per pixel (t_P = 2×t_PCLK).

4. Plug-in module verification (read before first power)#

Mandatory section. 18-pin OV7670 breakouts are mostly-but-not-always identical, three connectors here are orientation-sensitive, and the module's I/O supply question (4.3) affects whether 3.3 V operation is even in spec.

4.1 Pin-order check against the breakout silkscreen#

The carrier assumes the common 18-pin order (odd/even numbering matching the KiCad 2×9 footprint):

Procedure, breakout unplugged and carrier unpowered:

1. Read the breakout silkscreen for all 18 positions; write them down. Common variants differ in RESET/PWDN placement and in D-bus direction (D0 vs D7 at the connector end).
2. Buzz the breakout's 3V3 pin to its own LDO input/output and GND to its ground pour to confirm which corner is pin 1/2.
3. On the carrier, buzz J2 position 1 to the PMOD 3V3 pins and position 2 to GND; then verify the breakout's power pair lands there in the actual insertion orientation. A 2×9 socket accepts a 180°-rotated module: rotation puts 3V3 on PWDN and GND on RESET, and reverses the whole data bus — mark the correct orientation on both boards.
4. Spot-check three signal pins end-to-end: SIOC to J3 pin 7 (through the R12 node), PCLK to J3 pin 1 (through R9), D0 to J1 pin 1 (through R1).
5. Only then power up.

4.2 Plug-in key specifications (OmniVision OV7670/OV7171 datasheet v1.4)#

4.3 The I/O-voltage honesty note#

The OV7670's DC-characteristics table caps DOVDD (I/O) at 3.0 V (absolute max on I/O pins is DOVDD + 0.5 V). The common 18-pin breakout takes 3.3 V in and regulates some rails down — but breakouts differ in whether DOVDD is regulated (often to 2.8/3.0 V) or tied straight to the 3.3 V input. Two consequences to verify on the purchased unit:

• If the breakout regulates DOVDD (measure a regulator output feeding the sensor's F1/DOVDD ball region, or simply measure a data pin's high level): camera outputs will swing to ~2.8–3.0 V — comfortably above the ECP5's VIH for a 3.3 V bank — and host-driven 3.3 V inputs (XCLK, SIOC/SIOD, RESET, PWDN) exceed the sensor's DOVDD by ~0.3–0.5 V, at or beyond the absolute-max window. The 100 Ω/4.7 k series impedances limit the injected current, and hobby practice runs this way for years, but it is out of spec and must be recorded as such.
• If the breakout ties DOVDD to 3.3 V: levels match the PMOD perfectly but the sensor die itself runs its I/O rail above the 3.0 V DC-spec maximum — again common hobby practice, again out of spec.

Either way the carrier works in practice; the honest statement is that no combination of this commodity breakout and a 3.3 V PMOD is fully inside OmniVision's DC table. Measure the actual DOVDD and output-high levels during bring-up (section 9.B) and record them.

5. Component-by-component review#

#FLG01/#FLG02 are ERC power flags, not physical parts.

5.1 Connectors#

5.2 Series resistors on camera-driven lines#

5.3 Pull resistors, straps, and decoupling#

Host-driven XCLK is direct (no series R) — consistent with the family convention of protecting only module-driven lines; after layout, review whether a source-termination resistor on XCLK is warranted by trace length.

6. Datasheet summary and design interpretation#

Official references: OV7670/OV7171 datasheet v1.4, 2006 (MIT mirror). The SCCB protocol details are in OmniVision's separate "Serial Camera Control Bus (SCCB) Functional Specification"; the register map (PID/VER/MIDH/MIDL, CLKRC, COM7, etc.) is in the datasheet's register tables. OmniVision documents are distributed under NDA-era mirrors — record the exact revision used.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Complete section 4.1 (18-pin order) and 4.3 (DOVDD arrangement) against the purchased breakout before layout; record both in the repository.
• Close the three TBD: connector MPNs; export and availability-check the BOM.
• After layout, verify: J1↔J3 spacing against the ECP5 host's paired-PMOD pitch (the README release item); D0–D7 loosely length-matched with R1–R8 placed near the socket; PCLK routed away from XCLK (README) and landing on a clock-capable host pin; SCCB pull-ups near the socket; C1/C2 at the socket power pins.
• Confirm R14 pulls up and R15 pulls down — a swapped pair leaves the camera in reset/power-down by default and is invisible to ERC.
• Verify both PMOD plugs' pin-1 orientation against Pmod spec 1.2 Figure 2 (the family's placement recipe exists in pmod-common/PMOD-SPEC-NOTES.md).
• Plan FPGA constraints: PCLK as a clock (its own domain + CDC FIFO), input delay constraints derived from the 15/8 ns setup/hold numbers.

9. Ordered bench-test procedure#

Stop at the first abnormal result. This is the full-treatment sequence — each stage proves one layer before the next depends on it.

A. Unpowered checks#

1. Complete section 4.1 buzz-out and orientation marking (three connectors).
2. Resistance 3V3-to-GND at each PMOD plug, socket empty, then fitted.
3. Buzz all 11 series resistors end-to-end (D0–D7, PCLK, HREF, VSYNC) from J2 pad to PMOD pin; buzz SIOC/SIOD to J3 pins 7/8 and confirm ~4.7 k to 3V3 on each; confirm RESET_N ~10 k to 3V3 and PWDN ~10 k to GND.

B. Power, straps, and XCLK — no SCCB yet#

1. Plug into both host PMODs (verify seating across the pair). Power on.
2. Measure 3V3, supply current, RESET_N (3.3 V), PWDN (0 V).
3. Measure the breakout's DOVDD/regulator situation (section 4.3): probe a data pin's high level once the camera free-runs, and any visible LDO outputs. Record the numbers.
4. Enable the 24 MHz PLL output. Scope XCLK at the socket: frequency, duty 45–55 %, clean edges. XCLK must be verified before any SCCB attempt — the sensor needs a running clock to respond.
5. With XCLK running and default straps, the camera free-runs: confirm PCLK appears at J3 pin 1 (≈24 MHz) and VSYNC pulses at ≈30 Hz... if either is missing, resolve here before touching registers.

C. SCCB probe and ID read#

1. Pulse RESET_N low ≥1 ms with XCLK running; wait ≥1 ms.
2. Probe address 0x21 (write byte 0x42): expect ACK on the analyzer. No ACK → recheck XCLK first (the classic failure), then pull-ups, then pin order. Note SCCB read transactions differ slightly from pure I2C (some implementations don't ACK the read address byte identically) — judge by the returned data, not only the ACK bit.
3. Read PID (0x0A) expecting 0x76 and VER (0x0B) expecting 0x73; read MIDH/MIDL (0x1C/0x1D = 0x7F/0xA2). Record exact values — clones and relabeled sensors surface here.
4. Write/readback: set CLKRC (0x11) to divide PCLK by 2, verify PCLK halves; restore. This proves write, read, and a visible hardware effect in one step.
5. Reset again and confirm defaults return (RESET# clears all registers).

D. PCLK capture expectations and bus integrity#

1. Configure a known format (e.g., QVGA RGB565 via COM7 and the standard register set); wait 10 frames / 300 ms.
2. With a logic analyzer on PCLK/HREF/VSYNC/D0–D7 (short leads, ground at the socket): verify the frame skeleton against the datasheet — VSYNC pulse 3 t_LINE; 480 (VGA) or 240 (QVGA) HREF lines per frame; t_LINE = 784 t_P; two PCLK bytes per pixel in RGB565.
3. In the FPGA, capture on the documented PCLK edge and count: pixels per line, lines per frame, frames per second. These counters are the pass/fail gate before any image is judged.
4. Bit-plane sanity: enable the sensor's test-pattern output (color bars) and check each of D0–D7 toggles; a stuck bit means R1–R8/socket trouble and shows as banding.
5. CDC discipline: PCLK domain → line buffer/FIFO → system domain; verify no overflow/underflow counters increment over 1000 frames.

E. Live image and controls#

1. Stream frames to the host-side sink (VGA out, UART dump, or framebuffer readback). Color bars first; then live scene; check color channel order against the RGB565 byte-order figure (datasheet Fig. 11) rather than guessing.
2. RESET_N and PWDN line tests: PWDN high mid-stream — outputs stop, rail current drops (sensor <20 µA; LDO quiescent dominates); PWDN low — streaming resumes; full RESET_N cycle requires reconfiguration (registers cleared) — confirm your init code handles it.
3. 30-minute soak: frame counter continuity, CDC error counters, supply current, and socket temperature.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture is a faithful DVP capture design: every camera-driven line (all eleven of them) passes a series resistor, the dedicated SCCB bus gets fixed pull-ups, both control straps have defined defaults that the host can override, and the two-PMOD split puts the entire pixel bus on one connector. The datasheet-anchored constants (24 MHz XCLK, 0x42/0x43 SCCB, 0x76/0x73 ID, 784 t_P lines, 15/8 ns setup/hold) give the bench plan objective pass/fail gates. The principal risks are (1) three unkeyed/orientation-sensitive connectors, with the 2×9 rotation putting power onto PWDN/RESET; (2) the honest 3.3 V-versus-3.0 V I/O-rail gap on commodity breakouts, which must be measured and recorded rather than assumed away; (3) everything layout-dependent — paired-PMOD pitch, PCLK routing and clock-capable pin assignment, data-bus matching — which exists only as intent today; and (4) the absence of any fabrication or bench evidence at this revision.