← usb-c-pd-trigger

Circuit review & bench-test guide

Selectable USB-C PD trigger

Document purpose#

This document explains the usb-c-pd-trigger prototype at component level and turns the design evidence into a practical manual-review and bench-test plan. It is based on the implemented schematic, PCB, manufacturing BOM, selector harness specification, calculations, and QA evidence in this directory.

The board is still a prototype. Repository QA records 41 PASS, 5 CONDITIONAL, 18 OPEN, and 0 FAIL results. In particular, there is no recorded first-article bench result. Calculated and simulated values below are targets to verify, not proof that an assembled board is safe or conforming.

1. What the board does#

The board is a power-only USB Type-C Power Delivery sink. A five-position, two-pole external selector chooses a 5 V, 9 V, 12 V, 15 V, or 20 V ceiling. The HUSB238A negotiates autonomously, requests up to 3 A, and turns on a contract-authoritative P-channel MOSFET. A TPS259470A eFuse then applies a controlled ramp and adds current limiting, overload timing, overvoltage lockout, reverse-current blocking, and fault reporting.

It does not support USB data, PPS, AVS, EPR, or 5 A operation. The green LED means protected output voltage is present; it does not prove which PD voltage was negotiated or that 3 A is available.

Functional block diagram#

                          CC1 / CC2
USB-C J1 ─────────────────────┐
                             v
VBUS_RAW ───────────────> HUSB238A U1 <── two-pole selector J2
   │                         │ GATE          VSET + EN_N interlock
   ├── D1 TVS2200            v
   ├── D2 negative clamp   Q1 40 V P-MOSFET
   └── C1 input bypass        │
                              v
                           PD_VBUS
                              │
                              v
                       TPS259470A U2
                       eFuse / RCB / OVP
                              │
                              v
                            VOUT ──> J4 main output
                              ├────> J5 light-load header
                              ├────> J6 status/sense
                              └────> green output LED

2. Safety and scope boundaries#

• Use a certified, isolated USB-PD source or a current-limited PD source emulator. Do not connect this board directly to mains-derived circuitry.
• Use J4 and suitable 18–20 AWG wiring for high-current tests. Keep J5 at or below 0.5 A; solderless breadboards are not 3 A interconnects.
• Connect an earth-referenced oscilloscope ground only to board GND. Use a differential probe for high-side or floating measurements.
• Do not externally drive VOUT while USB is attached until reverse-energy behavior has been deliberately reviewed. Never tie two uncontrolled sources.
• Change selector position at no load first. The break-before-make EN_N pole is safety-critical; a damaged or incorrectly wired selector can request the wrong voltage.
• Do not perform IEC ESD/surge testing on an ordinary bench. The documented TVS/eFuse worst-case clamp margin is unresolved.
• A working negotiation is not USB-IF, EMC, safety, or environmental certification. Do not apply a USB logo based on prototype operation.

3. Power and control sequence#

1. With no cable, R6 holds Q1's gate at its source, so Q1 is off. U2 has no input and VOUT is off.
2. The selector connects SNK_VSET to one programmed resistance and grounds HUSB_EN_N only at a valid detent. Between detents EN_N opens.
3. The source detects the HUSB238A sink on CC1 or CC2 and initially supplies default USB-C VBUS.
4. U1 reads R3 as the 3 A request and the selected VSET resistance as the voltage ceiling, then negotiates the best acceptable fixed PDO.
5. After a valid contract, U1's GATE output pulls PMOS_GATE low through R5. Q1 connects VBUS_RAW to PD_VBUS; D3 limits excessive negative VGS.
6. U2 checks enable/UVLO and the R14/R15 OVLO divider. If valid, it ramps VOUT according to C3, limits current according to R17, and times overloads with C4.
7. C6 charges, D6 lights through R20, and the load can use J4. The sense divider R18/R19 reports a scaled VOUT on J6/TP4.

Why there are two series switches#

Q1 is controlled by the PD controller and is therefore the switch that says a contract has been accepted. U2 is a separate protection boundary. Removing Q1 would let the eFuse pass the source's default VBUS without contract authority; removing U2 would discard the precise inrush, overload, OVLO, fault, and always-on reverse-blocking functions. Their combined voltage drop and heating must be measured at 3 A.

4. Selector and external interfaces#

The intended external switch is a Grayhill 56A36-01-2-05N DP5T non-shorting selector wired to J2. Both commons must be open between detents.

An open VSET input means “highest voltage” for this controller, so the second pole is essential: it disables U1 between positions instead of allowing an open contact to become an accidental high-voltage request.

5. Component-by-component review#

5.1 Contract and main power path#

5.2 Transient, reverse, and gate protection#

5.3 U1 programming, indications, and bypass#

5.4 eFuse programming and output network#

5.5 Mechanical, shield, and option parts#

6. Datasheet summary and design interpretation#

Official references: HUSB238A product page, TPS25947 datasheet/product page, TVS2200 datasheet/product page, and DMP4015SSS product page. Check the latest revision and exact orderable suffix before procurement.

7. Expected values before bench testing#

8. Manual schematic and assembly review checklist#

• Confirm J1 CC1 and CC2 are separate and that all intended VBUS/GND pads are soldered. Inspect four shell stakes for adequate solder fill and retention.
• Verify exact U1/U2/Q1 orientation and orderable suffixes. Inspect U2's 2 mm QFN and D1 WSON with X-ray where available.
• Confirm D1, D2, D3, D4, D5, and D6 polarity.
• Measure R3 and R7–R11 values before installing the harness.
• Buzz J2 pin numbering from the board through the cable to the selector. Test both poles and confirm open-before-close between every adjacent position.
• Confirm R16, R21, D7, R23, and development headers are DNP for the core build.
• Inspect high-current copper transitions at J1, Q1, U2, and J4. Look for solder voiding, mask damage, whiskers, and insufficient via/pad wetting.
• Check that the J4 harness is pinned VOUT-to-load-positive and GND-to-return.

9. Ordered bench-test procedure#

Stop at the first abnormal result. Save raw captures with board serial number, source/cable identity, equipment ID, calibration date, ambient, and operator.

A. Unpowered inspection and resistance tests#

1. Disconnect USB, load, selector, and oscilloscope.
2. Inspect the assembly under magnification; complete the checklist above.
3. Measure VBUS_RAW-to-GND, PD_VBUS-to-GND, and VOUT-to-GND resistance in both meter polarities. Investigate a hard short before power.
4. Confirm no DC short from shell to GND; R22 should read about 1 MΩ after C8 settles when R23 is DNP.
5. Verify J2 selector continuity and break-before-make action with an ohmmeter.

B. First attach, no load#

1. Set selector to 5 V. Use a current-limited PD source/analyzer and no load.
2. Attach in one cable orientation. Capture CC, VBUS_RAW, PD_VBUS, VOUT, PMOS_GATE, and negotiated request as equipment permits.
3. Expect TP1 near 5 V, TP2 only after contract/GATE action, and a controlled TP3 ramp. Confirm the green LED and sense ratio.
4. Repeat after flipping the USB-C plug.
5. Repeat at 9, 12, 15, and 20 V. Confirm the analyzer's actual contract; do not infer voltage from selector position or LED state.

C. Selector safety and source mismatch#

1. With no load, rotate slowly through every detent while monitoring TP8, TP9, TP10, TP1, and TP3. EN_N must release and the path must disconnect between positions before a new request takes effect.
2. Try sources that lack selected PDOs and sources/cables that cannot provide 3 A. Record whether U1 selects a lower acceptable PDO or refuses the path, and verify the result is safe for the intended downstream load.
3. Do not proceed to loaded hot rotation until unloaded behavior is repeatable.

D. Load regulation and thermal soak#

1. Use J4, short heavy leads, remote DMM sense at J4, and an electronic load.
2. At each supported voltage, sweep 0 A, 0.1 A, 0.5 A, 1 A, 2 A, and 3 A while respecting the source/cable contract.
3. Record TP1, TP2, TP3, J4 voltage, input current, output current, Q1/U2/J1/J4 temperature, and FLT/PD_FAULT state.
4. Run 60 minutes at 3 A at worst intended ambient. Compare measured switch loss to the 0.540 W combined estimate and check connector/copper hot spots.

E. Dynamic, overload, and reverse tests#

1. Apply controlled load steps and capture VOUT deviation/recovery, source current, and fault outputs with bandwidth limits stated.
2. Increase load slowly through current limit, then test a controlled hard short using a safe fixture. Capture current limit, ITIMER, shutdown/retry, and temperature. Do not repeatedly short a hot board.
3. Repeat with representative added output capacitance; verify inrush and PD source stability rather than assuming the 61 mA fitted-cap estimate applies.
4. With USB absent, inject a current-limited voltage at VOUT below, equal to, and slightly above the intended rail as allowed by the test plan. Confirm U2 reverse blocking and that TP1/TP2 are not energized unexpectedly.

F. Release-only tests#

Perform source/cable interoperability, brownout/attach endurance, ESD, surge, EMC, product safety, and environmental compliance under controlled lab plans. The TVS2200/U2 clamp-margin question must be explicitly resolved before a surge claim or production release.

10. Troubleshooting map#

11. Bench record template#

12. Review conclusion#

The architecture is coherent: the HUSB238A owns the PD contract and Q1, while the TPS259470A provides a second, independent protection layer. The selector's two-pole interlock is not optional convenience—it prevents open VSET from becoming a high-voltage request. The principal release risks are unverified first-article behavior, 3 A thermal performance, hot selection and source interoperability, reverse/fault behavior, connector assembly quality, and the TVS2200 maximum-clamp versus U2 absolute-maximum mismatch.